1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device including a fuse structure and a pad structure exhibiting excellence in durability.
2. Description of the Background Art
In an attempt to improve speed and functionality of various types of electronic devices, a CMOS (complementary metal oxide semiconductor) device has been experiencing shrinkage according to a scaling law to enhance delay performance of a transistor. Aluminum having low resistance and good stability has continuously been used as an interconnect material of the CMOS device. However, shrinkage to a greater degree reduces the equivalent resistance of a transistor. As a result, limitations have been imposed on the performance of a transistor by the resistance of aluminum as an interconnect material. In response, aluminum has been replaced by copper in recent years as an interconnect material.
A conventional fuse structure will be discussed. Copper interconnect lines connected to gate interconnect lines, for example, are buried an interlayer insulating film. An aluminum interconnect line for forming a fuse structure is buried in a silicon oxide film provided on the interlayer insulating film. The copper interconnect lines are connected by the aluminum interconnect line. Provided on the silicon oxide film is polyimide or the like. An exemplary fuse structure is introduced in Japanese Patent Application Laid-Open No. 11-224900 (1999) (pp. 3-4 and FIGS. 1-8). According to the fuse structure introduced therein, a fuse link and an electrode pad are provided in the same layer on a Cu dual damascene interconnect line. Further, an interlayer insulating film and a passivation film form a two-layer structure on the fuse link.
Next, a conventional pad structure will be discussed. A copper interconnect line connected to a gate interconnect line, for example, is buried in an interlayer insulating film. An aluminum electrode pad is provided on the copper interconnect line to be in direct contact therewith. The electrode pad is partially buried in a silicon oxide film on the interlayer insulating film. Provided on the silicon oxide film is polyimide or the like.
The conventional fuse and pad structures cause the problems as follows. A semiconductor device may be subjected to a reliability test under high humidity and high temperature conditions. The reliability test under such conditions is generally called as a pressure-cooker test. When a semiconductor device having the conventional fuse and pad structures experiences the pressure-cooker test, water enters from a silicon oxide film, causing the problem such as deterioration in performance of an interconnect line of the semiconductor device, or expansion of the silicon oxide film itself.
In the fuse structure introduced in Japanese Patent Application Laid-Open No. 11-224900 (1999), a two-layer structure including an interlayer insulating film and a passivation film is formed on a fuse link. A silicon oxide film poor in resistance to humidity is thus prevented from being exposed to outside, to avoid the foregoing problems. On the other hand, a silicon nitride film used as a passivation film has absorbency of a laser beam for blowing. Further, such a silicon nitride film causes multiple reflection when it forms a composite with a silicon oxide film. These problems, when they occur on a fuse line, interferes with laser blow, causing difficulty in formation of a fuse structure exhibiting excellence in manufacturing margin. That is, only a silicon nitride film having excellence in permeability is desirably provided on a fuse line.